Power MOSFETs (metal oxide semiconductor field effect transistors) with trench field plates have been used as fast-switching power devices. The trench field plate provides charge compensation, allowing for much lower Rds(on)×A and lower gate-related FOM (figure of merit). The performance of such devices is limited by inhomogeneous switching effects of the device.
Such effects include inhomogeneous switching due to the distributed gate resistance. For example, parts of the chip in close vicinity to the gate pad follow a rapid change of the gate voltage that is much faster than for parts of the chip more distant to the gate pad. Furthermore, in difference to standard MOSFETs, the charging/discharging of the trench field-plate which provides charges to compensate for the drift region doping is inhomogeneous. In the case of fast transients, the field-plate charges too slowly due to the distributed resistance for its connections and the device may easily enter avalanche locally during the transients, leading to increased switching losses.
It is therefore advantageous to reduce the distributed gate resistance in general and improve the homogeneity of the distribution of the gate signal across the entire chip. Conventional solutions include widening the metal layers which connect the gates with the gate pad to reduce the electrical resistance. However, this measure is limited by the cell pitch. Also, widening the gate fingers requires additional active area. Such drawbacks also apply to equivalent measures for contacting the trench field-plates. Another conventional approach is the introduction of additional gate fingers, which reduces the active area and, thus, increases the Rds(on) of a given chip size. Still another conventional approach involves replacing the polysilicon often used as the gate material with a metal which might also be possible for the trench field-plate in the case of a MOSFET having such a structure. However, the use of metal for the device gate electrode and field-plate strongly impacts the subsequent process steps required to complete the chip fabrication since the maximum allowed temperature for a chip having a metal gate is reduced, which, in turn, limits the type of processing that can be carried out after formation of the metal gate.